FIG. 1 illustrates a 4T-2S image sensor circuit obtained by combining two image sensor circuits each including four transistors.
Referring to FIG. 1, a 4T-2S image sensor circuit 100 is obtained by combining two image sensor unit cells 10 and 20 each including four transistors. That is, reset transistors M12 and M22, conversion transistors M13 and M23, and selection transistors M14 and M24 are shared by two image sensor circuits each including four transistors. The 4T-2S image sensor circuit 100 senses and transmits electric charges corresponding to image signals generated by two photodiodes PD1 and PD2 by using three shared transistors MC2, MC3, and MC4 and two transmission transistors M11 and M21.
Here, since a reset signal Rx12 applied to a gate of a reset transistor MC2 is enabled when one of two charge transmission control signals Tx1 and Tx2 applied to gates of the transmission transistors M11 and M21 is enabled, the reset signal Rx12 is denoted by using ‘12’. Similarly, a selection signal Sx12 applied to a gate of a selection transistor MC4 is denoted by using ‘12’.
As described above, a single 4T-2S image sensor circuit obtained by combining two image sensor circuits each including four transistors may be laid out in various manners. A conventional combined cell obtained by combining four cells has a structure in which a floating node is shared through four photodiodes and four transmission transistors connected to the four photodiodes. Accordingly, when a problem occurs in a cell among the four cells, the other cells cannot be used. This largely influences yields of products.